The present invention relates to semiconductor integrated circuits having a standard voltage wire established at a standard voltage other than supply voltage and ground voltage.
Semiconductor integrated circuits, especially MOS dynamic RAMs, have progressed further and further to a high degree of integration and capacity. Consequently, the amount of electric charge for charging and discharging bit lines connected to memory cells has become quite large. Thus, the fluctuation of supply voltages V.sub.cc and V.sub.ss, namely, power supply noise, has also increased, so that operation of various circuits suffer undesirable effects.
In reference to an address buffer circuit that is one of the sense circuits in an MOS dynamic RAM, the problems encountered may be illustrated in the following discussion taken together with FIG. 1.
FIG. 1 is an example of the conventional address buffer circuit. This address buffer circuit has, as its main elements, a first sense MOS transistor Q.sub.1 and a second sense MOS transistor Q.sub.2. The first MOS transistor Q.sub.1 has a gate input from address signal A.sub.in which feeds thereto one of "H" or "L" voltage levels, and the second MOS transistor Q.sub.2 has a gate input from a standard voltage V.sub.R intermediate "H" and "L" voltage levels.
The voltage levels at nodes N.sub.1, N.sub.2 of a flip-flop 1 consisting of MOS transistors Q.sub.3 through Q.sub.6 are determined in accordance with the difference of conductance between Q.sub.1 and Q.sub.2, which is brought about by the input noise difference described above. These levels are amplified with a first stage amplifier 2 consisting of MOS transistors Q.sub.7 through Q.sub.11, and then, amplified again with a second stage amplifier 3 comprising MOS transistors Q.sub.12 through Q.sub.15 and boosting capacitors C3 and C4. As a result, address output A.sub.N and inverted output A.sub.N are provided. MOS transistors Q.sub.18 through Q.sub.21, are transfer gates. The capacitor C.sub.1 is an element for preventing undershooting, and capacitor C.sub.2 is provided for balancing.
The standard voltage V.sub.R is generated by the resistance division network of resistors R.sub.1 and R.sub.2 connected in series between V.sub.cc and V.sub.ss as shown in FIG. 1. The number 4 denotes a standard voltage wire.
In the foregoing construction, the standard voltage V.sub.R is not usually generated nearby the sense MOS transistor Q.sub.2 to which V.sub.R is input, but the standard voltage wire 4 is usually formed on the chip in a position remote from Q.sub.2. Especially, in cases in which the same standard voltage V.sub.R is supplied to a plurality of circuits, the standard voltage wire 4 is extended to a relatively long length in relation to the chip component sizes. Moreover, the standard voltage wire 4 is connected at one end thereof to the electric potential provided by the resistance division network, and thus, the wire 4 is almost in a floating state.
As is common, when other signal wires are arranged adjoining the standard voltage wire 4, the potential of the standard voltage V.sub.R will fluctuate in accordance with the coupling capacitance generated by the close wires. Therefore, malfunction of the address buffer circuits is likely to occur. On the other hand, the potential fluctuation of V.sub.ss and V.sub.cc causes fluctuations of the substrate potential. These fluctuations produce further variations of the standard voltage V.sub.R, and this variation of the power level also is likely to cause malfunction of the address buffer circuits.